As scaling conventional planar complementary metal-oxide semiconductor (CMOS) becomes increasingly challenging, several non-planar device structures have been considered. One such non-planar device structure is a tri-gate field effect transistor (FET). A tri-gate FET achieves superior short channel characteristics from the electrostatics that the geometry of the structure provides.
However, one issue with tri-gate FETs is that small width/height dimensions are required to obtain good short channel control. There are two issues here. First, variation due to process control and roughness, i.e., line edge roughness (LER). The second is effective total device width, which is lessened as the device width and height are reduced.
Therefore, improved FET fabrication techniques would be desirable.